In these days, a liquid crystal display (LCD) device, featured by thin thickness, lightweight and low power consumption, has come into widespread use as a display device, and is predominantly used as a display in a mobile telephone set, such as a mobile phone or a cellular phone, a PDA (Personal Digital Assistant) or in a mobile equipment, such as notebook PC. Only recently, the technology for a large screen size liquid crystal display or the technology adapted for a moving picture has made progress such that it becomes possible to manufacture not only a display for a mobile device but a fixed large screen size display device or a large screen liquid crystal TV set. For a liquid crystal display, a liquid crystal display of an active matrix driving system that allows for high definition display is being used. A display device of the active matrix driving system, making use of an organic light-emitting diode (OLED), is also being developed as thin type display device.
Referring to FIGS. 24A to 24C, a typical arrangement of a thin type display device of the active matrix driving system (liquid crystal display and an organic light emitting diode display) will be briefly described. FIG. 24A is a block diagram showing essential portions of a thin type display device. FIG. 24B is a diagram showing essential portions of a unit pixel of a display panel provided in a liquid crystal display device. FIG. 24C is a diagram showing essential portions of a unit pixel of a display panel provided in an organic light emitting diode display device. It is noted that the unit pixel of each of FIGS. 24B and 24C is shown by a schematic equivalent circuit.
Referring to FIG. 24A, a thin type display device of the active matrix driving system includes a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970 and a data driver 980. The display panel 960 includes a plurality of unit pixels which are arranged in a two dimensional matrix, and each of which includes a pixel switch 964 and a display element 963. For example, in a color SXGA (Super eXtended. Graphics Array) panel, including 1280×3 pixel columns by 1024 pixel rows, a plurality of scan lines 961 and a plurality of data lines 962 are arrayed in a latticed configuration. The scan line 961 provides a scan signal output from the gate driver 970 to the unit pixel, while the data line 962 provides a gray scale voltage signal from the data driver 980 to the unit pixel. It is noted that the gate driver 970 and the data driver 980 are controlled by the display controller 950, which also supplies a necessary clock signal CLK and control signals. Video data is supplied as a digital signal to the data driver 980. The power supply circuit 940 supplies necessary power necessary to the data driver 980 and to the gate driver 970. The display panel 960 includes a semiconductor substrate. In particular, in a large screen display device, the semiconductor substrate composed of an insulating substrate, such as substrate formed of glass or plastics, on which pixel switches are formed by thin film transistors (TFTs), is in a widespread use.
In the above display device, the scan signal controls on and off of the pixel switch 964, such that, when the pixel switch 964 is turned on, a gray scale voltage signal corresponding to video data, is applied to a display elements 963. The luminance of the display element 963 is varied in response to the gray scale voltage signal to display an image.
Each screen image data is rewritten in one frame period which is approximately 0.017 second in case of 60 Hz driving. Each scan line 961 sequentially selects sequentially a pixel row (pixel switches 964 are turned on) on a per line basis and in a selected period, each data line 962 supplies a gray scale voltage signal via the pixel switch 964 to each display element 963. There are cases where a plurality of pixel rows corresponding to a plurality of scan lines are selected simultaneously, or where the frame frequency exceeds 60 Hz.
In the liquid crystal display device, the display panel 960 includes a semiconductor substrate, an opposite substrate and a liquid crystal sealed in a gap between the two substrates, as shown in FIGS. 24A and 24B. The semiconductor substrate includes unit pixels which are arranged in a matrix array, and each of which includes the pixel switch 964 and a transparent electrode 973, and the opposite substrate includes a transparent electrode 974 the size of the opposite substrate. It is noted that the display element 963 that makes up the unit pixel includes a pixel electrode 973, an opposite substrate electrode 974, a liquid crystal capacitance 971 and an auxiliary capacitance 972. A backlight as light source is provided on the reverse surface of the display panel.
When the pixel switch 964 is turned on by the scan signal supplied on the scan line 961, the gray scale voltage signal from the data line 962 is applied to the pixel electrode 973. The transmission of light from the backlight, passing through the liquid crystal, is changed due to a potential difference between each pixel electrode 973 and the opposite substrate electrode 974. This potential difference is maintained for a certain time interval by the liquid crystal capacitance 971 and the auxiliary capacitance 972 even after the pixel switch 964 for display is turned off (made non-conductive).
It is noted that, in driving the liquid crystal device, the voltage polarity of each pixel electrode 973 is switched to be positive or negative with respect to a common voltage of the opposite substrate electrode 974, usually on a per-frame period basis, in order to prevent liquid crystal from deterioration (inverted driving). Typical inverted driving includes dot inversion driving which provides for different voltage polarities between neighboring pixels, and column inversion which provides for different voltage polarities between neighboring pixels columns. In the dot inversion driving, gray scale voltage signals of different voltage polarities are output on the data line 962 from one selection period (data period) to the next. In the column inversion driving, the gray scale voltage signal is output to the same voltage polarity for respective selection periods (respective data periods) within one frame period, and gray scale voltage signals of different voltage polarities are output from one frame period to the next.
In the organic light emitting diode, the display panel 960 is formed by a semiconductor substrate on which there are arrayed unit pixels in a matrix configuration, as shown in FIG. 24A. Each unit pixel includes a pixel switch 964, an organic light emitting diode 982 and a thin film transistor (TFT) 981. The organic light emitting diode 982 is an organic film sandwiched between two thin film electrode layers. The thin film transistor (TFT) 981 controls a current supplied to the organic light emitting diode 982. The TFT 981 and the organic light emitting diode 982 are connected in series between power supply terminals 984 and 985 which are supplied with different power supply voltages. There is also provided an auxiliary capacitance 983 that holds a control terminal voltage of the TFT 981. A display element 963 corresponding to one pixel includes the TFT 981, organic light emitting diode 982, power supply terminals 984, 985 and the auxiliary capacitance 983.
When the pixel switch 964 is turned on by the scan signal supplied on a scan line 961, the gray scale voltage signal from the data line 962 is applied to the control terminal of the TFT 981. The current corresponding to the gray scale voltage signal is supplied by the TFT 981 to the organic light emitting diode 982, which emits light with luminance according to the current, thereby making display. The gray scale voltage signal, applied to the control terminal of TFT 981, is kept for a certain time interval by the auxiliary capacitance 983, even after the pixel switch is turned off, thereby maintaining the state of light emission. The pixel switch 964 and the TFT 981 are shown to be formed by Nch transistors, however, these may also be formed by Pch transistors. The organic light emitting diode may also be connected to the power supply terminal 984. It is noted that, in driving the organic light emitting diode display device, no driving inversion, as used in the liquid crystal device, is necessary, such that a gray scale voltage signal, corresponding to the pixel, is output on a per selection period (one data period) basis.
In addition to the display configuration of the organic light emitting diode display device, in which display is in response to the gray scale voltage signal from the data line 962, there is another configuration in which display is done in response to a gray scale current signal output from a data driver. The display configuration disclosed herein is restrictively in response to the gray scale voltage signal output from the data driver. It should be noted however that the present invention is not limited to this display configuration.
In FIG. 24A, it suffices that the gate driver 970 supplies a scan signal which is at least a binary signal. On the other hand, the data driver 980 has to drive each data line 962 with multi-level gray scale voltage signals correlated with the number of gray scales. Hence, the data driver 980 includes an output circuit that amplifies a gray scale voltage signal corresponding to video data, and that outputs the so amplified signal to the data line 962.
In mobile equipment for high-end use, notebook PC, monitors or television receiver, having a thin type display device, there is recently an increasing need for higher image quality. More specifically, there is about to be raised a demand for multi-color display for not less than 16800000 colors for video data with 8 bits for each of R, G and B, for higher quality for moving pictures, and for three-dimensional display. In order to meet such demand, the frame frequency, that is, the driving frequency of rewriting each picture image, has to be increased to 120 Hz or even higher. If the frame frequency is increased by a factor of N, each data output period is reduced to 1/N.
It is demanded of the data driver of the display device to output a voltage with a high precision correlated with the increase in gray levels as well as to drive a data line at a high speed. It is thus demanded of an output circuit of the data driver 980 to have a high driving capability in order to charge or discharge the data line capacitance at a high speed. On the other hand, to ensure uniformity in writing of a gray scale voltage signal in the display element, there is also raised a demand for symmetry in the slew rate of the data line driving waveform at the time of charging/discharging. However, current consumption is increased as the driving capability of the output circuit is raised. Thus, the output circuit also suffers the problem of increased power consumption and heat generation.
The following techniques are disclosed to implement high speed driving of the data line of the display device.
FIG. 25 is a drawing cited from FIG. 1 of Patent Document 1 (JP Patent Kokai Publication No. JP-P2007-208316A). This output circuit includes a differential input stage 50, including a P-type differential input stage 60A and an N-type differential input stage 60B, a current mirror 70, a push-pull output stage 80, a first auxiliary current source 60C, a second auxiliary current source 60D, a control circuit 90 and an output auxiliary circuit 100. The P-type differential input stage 60A includes a first current source 51, connected between the power supply VDD and a node N1, and PMOS transistors (Pch transistors) 61 and 62 that have coupled sources connected to the node N1, drains connected to nodes N13 and N14, respectively and gates connected to IN and OUT, respectively.
The N-type differential input stage 60B includes a second current source 52, connected between a node N2 and a power supply VSS, and NMOS transistors (Nch transistors) 63 and 64 that have sources connected in common to a node N2, drains connected to nodes N11 and N12, respectively and gates connected to IN and OUT, respectively.
The current mirror 70 causes a first power supply current to flow through nodes N12 and N14, while causing a second power supply current, correlated with the first power supply current, to flow through nodes N11 and N13. In the current mirror 70, a PMOS transistor 71, a resistor 73 and an NMOS transistor 75 are connected in series between VDD and VSS, while a PMOS transistor 72, a resistor 74 and an NMOS transistor 76 are connected in series between VDD and VSS. The PMOS transistor 71 has its gate and drain coupled together, while the NMOS transistor 75 has its gate and drain coupled together. The NMOS transistors 75 and 76 have gates coupled together.
A push-pull output stage 80 includes a PMOS transistor 81 that has source connected to the power supply VDD, a gate connected to a node N11 and a drain connected to OUT, and an NMOS transistor 82 that has a source connected to VSS, a gate connected to N13 and a drain connected to OUT. A phase compensation capacitance 83 is connected between a gate (node N11) and a drain of the PMOS transistor 81. A phase compensation capacitance 84 is connected between a gate (node N13) and a drain of the NMOS transistor 82.
The first auxiliary current source 60C includes a third current source 53 that has one end connected to the power supply VDD, and a PMOS transistor 65 that has a source connected to the other end of the third current source 53, a gate connected to a node N15 and a drain connected to a node N1. The first auxiliary current source 60C also includes a PMOS transistor 65-9 that has a source connected to the other end of a third current source 53, a gate connected to a node N17 and a drain connected to a node N1. The second auxiliary current source 60D includes a fourth current source 54 that has one end connected to the power supply VSS, and an NMOS transistor 66 that has a source connected to the other end of the fourth current source 54, a gate connected to a node N16 and a drain connected to a node N2. The second auxiliary current source 60D also includes an NMOS transistor 66-10 that has a source connected to the other end of a fourth current source 54, a gate connected to a node N18 and a drain connected to a node N2.
The control circuit 90 includes a controller 93, an output stage auxiliary unit 94 and current sources 91 and 92. Of these, the current source 91, controller 93 and the current source 92 are connected in series between VDD and VSS. In addition, an output stage auxiliary unit 94 is connected between nodes N11 and N13. The controller 93 includes an NMOS transistor 93-1 (first detection transistor) that has a drain connected to a node N15, a gate connected to IN and a source connected to OUT, and a PMOS transistor 93-2 (second detection transistor). The PMOS transistor 93-2 has a source connected to OUT, a gate connected to IN and a drain connected to a node N16. The controller 93 detects the potential difference between IN and OUT and, based on the result of detection of the potential difference between IN and OUT, controls the gate potentials of the PMOS transistors 65 and 94-7 and the NMOS transistors 66 and 94-8.
The output stage auxiliary unit 94 includes a PMOS transistor 94-7 that has a source connected to node N11, a gate connected to N15 and a drain connected to OUT, and a PMOS transistor 94-8 that has a source connected to node N13, a gate connected to node N16 and a drain connected to OUT.
The output auxiliary circuit 100 includes a current source 101, connected between the power supply VDD and node N17, and a current source 102 connected between node N18 and the power supply VSS. The output auxiliary circuit 100 also includes a diode-connected PMOS transistor 113 that has a source connected to the power supply VDD, and a PMOS transistor 111 that has a source connected to the drain of the PMOS transistor 113, a gate connected to node N11 and a drain connected to node N18. The output auxiliary circuit 100 also includes a PMOS transistor 114 that has a source connected to the drain of PMOS transistor 113, a gate connected to node N17 and a drain connected to node N11, and a diode-connected NMOS transistor 116 that has a source connected to the power supply VSS. The output auxiliary circuit 100 also includes an NMOS transistor 112 that has a source connected to the drain of the NMOS transistor 116 that has a gate connected to node N13 and a drain connected to node N17, and an NMOS transistor 115 that has a source connected to a drain of the NMOS transistor 116, a gate connected to node N18 and a drain connected to node N13.
The PMOS transistor 111 controls the voltage at the gates (node N18) of NMOS transistors 66-10 and 115, based on the potential at the node N11, while managing control to fix the potential at node N13 by the NMOS transistor 115. The NMOS transistor 112 operates complementarily with respect to the PMOS transistor 111 to control the gates of PMOS transistors 65-9 based on the potential at the node N13 as well as to fix the potential at the node N11 by the PMOS transistor 114.
The control circuit 90 exercises control to detect the input/output potential difference (93) at the time of input variations to turn on output stages 81 and 82 deeply and to increase the current in the differential input stage 50 to raise the slew rate (amount of output voltage variation per unit time).
The output auxiliary circuit 100 suppresses a through current (short circuit current) in the output stage 80.
When the input terminal is at the same voltage as the output terminal, the transistors 93-1 and 93-2 of the controller 93 and the transistors 94-7 and 94-8 of the output stage auxiliary unit 94 are all turned off. When the voltage at the input terminal IN is markedly changed towards the VDD side with respect to the voltage at the output terminal OUT, the NMOS transistor 93-1 is turned on to pull up the gate of the PMOS transistor 94-7 (node N15) to the voltage at the output terminal OUT. This causes the PMOS transistor 94-7 to be turned on to pull down the gate voltage of the PMOS transistor 81 of the output stage 80 (node N11), instantaneously. The PMOS transistor 81 is turned on to quickly charge the output terminal OUT from the power supply VDD to approach to the voltage at the input terminal IN.
When the gate of the PMOS transistor 94-7 (node N15) is pulled down at this time, the PMOS transistor 65 of the first auxiliary current source unit 60C of the differential input stage 50 is turned on. The current in the third current source 53 is added to the current in the first current source 51 in driving the PMOS differential pairs 61 and 62 to accelerate charging/discharging at the capacitance 84.
When the voltage at the output terminal OUT approaches to that at the input terminal IN, the NMOS transistor 93-1 of the controller 93 is turned off. Then, the transistor 94-7 of the output stage auxiliary unit 94 is also turned off to halt the charging at the output terminal OUT automatically. The voltage at the node N15 is the power supply voltage VDD and the PMOS transistor 65 of the first auxiliary current source 60C is turned off.
When the voltage at the input terminal IN is changed towards the VDD side, the transistor 93-2 of the controller 93, NMOS transistor 94-8 of the output stage auxiliary unit 94 and the NMOS transistor 66 of the second auxiliary current source 60D are off. If, on the other hand, the voltage at the input terminal IN is markedly changed towards the VSS side, the transistor 93-2 of the controller 93 and the NMOS transistor 94-8 of the output stage auxiliary unit 94 are turned on to pull up the gate voltage (node N16) of the NMOS transistor 82 of the output stage 80 instantaneously to quickly discharge the output terminal OUT. As the voltage at the output terminal OUT approaches to that at the input terminal IN, the discharging halts automatically. The NMOS transistor 66 of the second auxiliary current source 60D of the differential input stage 50 is also turned on as long as the transistor 93-2 of the controller 93 is in operation. The driving current of the Nch differential pair 63 and 64 is increased to a current value which is the sum of the current at the second current source 52 and that at the fourth current source 54 to accelerate the charging/discharging at the capacitance 83. At this time, the NMOS transistor 93-1 of the controller 93, PMOS transistor 94-7 of the output stage auxiliary unit 94 and the PMOS transistor 65 of the first auxiliary current source 60C are all turned off.
The control circuit 90 is in operation when the voltage at the input terminal IN is markedly changed with respect to the voltage at the output terminal OUT to cause the output terminal OUT to approach quickly to the voltage at the input terminal IN. On the other hand, the auxiliary current sources 53 and 54 of the differential input stage 50 are connected to the respective differential pairs, depending on the operation of the control circuit 90, such as to accelerate charging/discharging of the capacitances 83 and 84. This allows driving the output terminal OUT quickly to a voltage that will prevail after change of the voltage at the input terminal IN.
The phase compensation capacitances 83 and 84, respectively connected between the gates and the drains of the output stage transistors 81 and 82 (output terminal OUT), are of sufficiently large capacitance values as compared with the parasitic capacitances of the elements.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2007-208316A    [Patent Document 2] JP Patent Kokai Publication No. JP-A-6-326529